1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a delay line.
2. Description of Related Art
In a semiconductor device that operates in synchronism with a clock signal such as a synchronous DRAM (Dynamic Random Access Memory), an internal clock signal that is phase-controlled is required in some cases. The phase-controlled internal clock signal is generated mainly by a DLL (Delay Locked Loop) circuit (see Japanese Patent Application Laid-open No. 2009-284266). The DLL circuit secludes a delay line that delays an internal clock signal and its amount of delay is specified by a count value output from a counter circuit.
In the DLL circuit described in Japanese Patent Application Laid-open No. 2000-284266, a coarse-adjustment delay circuit having a coarse adjustment pitch of adjusting the delay amount and a fine-adjustment delay circuit having a fine adjustment pitch of adjusting the delay amount are connected in series. The DLL circuit can thereby make a fine adjustment of the delay amount while securing a sufficiently wide adjustment range of the delay amount. Although not related to the DLL circuit, Japanese Patent Applications Laid-open Nos. H10-144074 and S62-299113 disclose a one-shot pulse generation circuit.
However, an ordinary fine-adjustment delay circuit requires a voltage generation circuit for generating an analog voltage because the fine-adjustment delay circuit is as interpolator circuit that uses the analog voltage. Furthermore, the ordinary fine-adjustment delay circuit is unable to obtain a desired delay amount without sufficiently ensuring the stability of the analog voltage because the delay amount changes according to unintended variations in the analog voltage. These problems occur not only to the delay line used in the DLL circuit but also to all delay lines for which it is necessary to highly accurately control the delay amount of clock signals.